Mentor Graphics Updates VStationTBX Verification Accelerator, Delivering Full Language Support for System C
WILSONVILLE, Ore.—(BUSINESS WIRE)—April 15, 2004—
Mentor Graphics Corporation today announced an updated
version of its VStation(TM) TBX verification accelerator that delivers
full support for the leading system design languages. The VStationTBX
tool now accelerates test benches in System C, generating verification
results more than 500 times faster than co-simulation methods, and
more than 10,000 times faster than software simulation. The updated
VStationTBX tool extends the Mentor Graphics(R) Scalable
Verification(TM) Platform, an interconnected suite of tools providing
system-level verification and debugging for complex
application-specific integrated circuit (ASIC) and system-on-chip
(SoC) designs.
The VStationTBX tool, through its test bench compiler, compiles
behavioral hardware description language (HDL) along with RTL,
allowing designers to quickly map behavioral Verilog testbenches and
memories into the VStationPRO emulator. This eliminates the
performance bottlenecks and re-modeling effort of co-simulation,
allowing design teams to save months on testbench execution and
creation. In addition, the VStationTBX tool provides automated support
for transaction-based modeling methods and standard verification
languages such as SystemC, combining accelerated verification with the
power of abstraction, and directed random testing.
By combining the test bench compilation and transaction-based
verification capabilities in the VStationTBX tool, designers can
incrementally improve the effectiveness, reusability and performance
of their current testbenches, increasing design engineer efficiency
and providing a scalable testbench methodology from software
simulation to high-performance acceleration.
"The improvements we are making to the VStationTBX tool will allow
customers to use hardware to speed complex system verification tests,"
said Eric Selosse, vice president and general manager of the Mentor
Graphics Emulation Division. "Our verification acceleration products
have been a key component of more than 50 successful tapeouts so far
and are facilitating the migration to the widespread use of
transaction-based verification and directed random testing together
with acceleration, helping customers to shorten their verification
cycles and get quality products to market faster."
About VStationTBX
The VStationTBX (TestBench-XPress) tool is a verification
accelerator for design and verification teams who are dissatisfied
with the performance and productivity of their software simulations.
The VStationTBX tool is based on Mentor's unique TestBench Compiler
and automated transaction technology, revolutionizing the quality of
verification performance by providing access to minutes of real-time
verification and high-level test benches.
Unlike traditional co-simulation which is limited in performance,
the VStationTBX tool compiles 2-state behavioral Verilog, including
behavioral memory models into the emulator, executing it directly. The
VStationTBX tool's TestBench Compiler provides an initial 20-200x
performance increase for existing verification environments.
Once a customer is enjoying this initial performance boost, the
VStationTBX tool enables them to incrementally migrate to higher
abstraction, performance and productivity by using Mentor's third
generation of transaction-based technology to smoothly connect
abstract C or hardware verification language (HVL) models to their
design and test bench components in the emulator.
The VStationTBX tool's combination of testbench compilation and
high speed automated transaction interface results in performance of
1,000 to 10,000 times simulation with high verification productivity
and reuse. The VStationTBX tool is the first tool to offer this
incremental migration capability. The VStationTBX tool was recently
highlighted by MIPS Technologies in the verification of its 24k family
of cores.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$675 million and employs approximately 3,700 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: www.mentor.com.
Mentor Graphics is a registered trademark of Mentor Graphics Corp.
VStationTBX and Scalable Verification are trademarks of Mentor
Graphics. All other company and/or product names are the trademarks
and/or registered trademarks of their respective owners.
Contact:
Mentor Graphics
Larry Toda, 503-685-1664
larry_toda@mentor.com
or
Weber Shandwick
Hayley Luz, 503-552-3726
hluz@webershandwick.com
